Build

Using Vitis

Refer this

Using Command line

  1. Create .bif file eg: output.bif

$ vi output.bif

Contents of .bif file:

/* Linux */
the_ROM_image:
{
 [bootloader] <xsct_ws/zynq_fsbl/Release/-path>zynq_fsbl.elf
 <xsct_ws/spec7_custom/hw/-path to bitstream>/spec7_custom.bit
 <path-to-u-boot>/u-boot.elf
}

output.bif with offset support for two designs

/*Linux*/
the_ROM_image:
{
   [bootloader] zynq_fsbl.elf
   tandem_gateware.bit
   u-boot.elf
   [offset = 0x20000000]reference_gateware.bit
  }

  1. Build using bootgen command:

Setup environment

$ source /tools/Xilinx/Vitis/2019.2/settings64.sh

Run bootgen

bootgen -image output.bif -arch zynq -w -o BOOT.bin

Use this image to load in QSPI from command line

program_flash -f BOOT.bin -fsbl </path/to/fsbl>/zynq_fsbl.elf  -flash_type qspi-x8-dual_parallel  -blank_check -url tcp:localhost:3121

Using Script

BOOT.bin can be generated by automating above steps. Refer ../sw/boot Build.sh script in spec7 ohwr repo , run:

$ ./Boot_Build.sh -t -r -o -u -h

Usage: $0 -t {Tandem_bitfile} -r {Reference_bitfile} -o {Memory_Offset};
        -t {Tandem_bitfile} location of the bitfile used in tandem PCIe boot. Default is the most recent bitfile in spec7/hdl/syn/ containing the word "tandem".;
        -r {Reference_bitfile} location of the bitfile used in the reference design. Default is the most recent bitfile in spec7/hdl/syn/ containing the word "ref".;
        -o {Memory_Offset} the DDR3 Memory offset where the reference design is loaded into. Default is 0x1000000.;
        -u {uboot uart channel} The uart channel number where Cout and Cin is directed. Default is 0.;
        -h Prints this help message.;

It will generate all require components i.e FSBL, U-boot, Boot.bin in /output directory